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TM
HD-6402/883
CMOS Universal Asynchronous Receiver Transmitter (UART)
Description
The HD-6402/883 is a CMOS UART for interfacing computers or microprocessors to an asynchronous serial data channel. The receiver converts serial start, data, parity and stop bits. The transmitter converts parallel data into serial form and automatically adds start, parity and stop bits. The data word length can be 5, 6, 7 or 8 bits. Parity may be odd or even. Parity checking and generation can be inhibited. The stop bits may be one or two or one and one-half when transmitting 5-bit code. The HD-6402/883 can be used in a wide range of applications including modems, printers, peripherals and remote data acquisition systems. Utilizing the Intersil advanced scaled SAJI IV CMOS process permits operation clock frequencies up to 8.0MHz (500K Baud). Power requirements, by comparison, are reduced from 300mW to 10mW. Status logic increases flexibility and simplifies the user interface.
March 1997
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * 8.0MHz Operating Frequency (HD-6402/883B) * 2.0MHz Operating Frequency (HD-6402/883R) * Low Power CMOS Design * Programmable Word Length, Stop Bits and Parity * Automatic Data Formatting and Status Generation * Compatible with Industry Standard UARTs * Single +5V Power Supply * CMOS/TTL Compatible Inputs
Ordering Information
PACKAGE CERDIP TEMPERATURE RANGE -55oC to +125oC 2MHz = 125K BAUD HD1-6402R/883 8MHz = 500K BAUD HD1-6402B/883 PKG. NO. F40.6
Pinout
HD-6402/883 (CERDIP) TOP VIEW
VCC NC GND RRD RBR8 RBR7 RBR6 RBR5 RBR4 RBR3 RBR2 RBR1 PE FE OE SFD RRC DRR DR RRI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 TRC 39 EPE 38 CLS1 37 CLS2 36 SBS 35 PI 34 CRL 33 TBR8 32 TBR7 31 TBR6 30 TBR5 29 TBR4 28 TBR3 27 TBR2 26 TBR1 25 TRO 24 TRE 23 TBRL 22 TBRE 21 MR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
FN2953.1
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HD-6402/883 Control Definition
CONTROL WORD CLS 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 CLS 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 PI 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 EPE 0 0 1 1 X X 0 0 1 1 X x 0 0 1 1 X x 0 0 1 1 X x SBS 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 START BIT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CHARACTER FORMAT DATA BITS 5 5 5 5 5 5 6 6 6 6 6 6 7 7 7 7 7 7 8 8 8 8 8 8 PARITY BIT ODD ODD EVEN EVEN NONE NONE ODD ODD EVEN EVEN NONE NONE ODD ODD EVEN EVEN NONE NONE ODD ODD EVEN EVEN NONE NONE STOP BITS 1 1.5 1 1.5 1 1.5 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
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HD-6402/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage Applied. . . . . GND -0.5V to VCC +0.5V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Typical Derating Factor . . . . . . . . . . . 1mA/MHz Increase in ICCOP
Thermal Information
Thermal Resistance JA JC CERDIP Package . . . . . . . . . . . . . . . . 50oC/W 12oC/W Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . .-55oC to +125oC
TABLE 1. HD-6402/883 D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 2.3 -1.0 3.0 VCC -0.4 -1.0 MAX 0.8 1.0 0.4 1.0 100 UNITS V V A V V V A A
D.C. PARAMETER Logical ``1'' Input Voltage Logical ``0'' Input Voltage Input Leakage Current Logical ``1'' Output Voltage Logical ``1'' Output Voltage Logical ``0'' Output Voltage Output Leakage Current Standby Supply Current
SYMBOL VIH VIL IID VOH VOH VOL IO ICCSB
CONDITIONS VCC = 5.5V VCC = 4.5V VIN = GND or VCC, VCC = 5.5V IOH = -2.5mA, VCC = 4.5V (Note 1) IOH = -100A VCC = 4.5V (Note 1) IOL = +2.5mA, VCC = 4.5V (Note 1) VO = GND or VCC, VCC = 5.5V VIN = GND or VCC; VCC = 5.5V, Output Open
TABLE 2. HD-6402/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS HD-6402/883R TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 150 150 50 60 MAX 2.0 160 LIMITS HD-6402/883B MIN 75 150 20 20 MAX 8.0 35 UNITS MHz ns ns ns ns ns
A.C. PARAMETER Clock Frequency Pulse Widths, CRL, DRR, TBRL Pulse Width MR Input Data Setup Time Input Data Hold Time Output Enable Time NOTE:
SYMBOL (1) fCLOCK (2) tPW (3) tMR (4) tSET (5) tHOLD (6) tEN
(NOTE 1) CONDITIONS VCC = 4.5V CL = 50pF
GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
1. Interchanging of force and sense conditions is permitted. 2. Tested with input levels of VIH = 2.76V and VIL = 0.4V. Rise and fall times are driven at 1ns/V.
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HD-6402/883
TABLE 3. HD-6402/883 ELECTRICAL PERFORMANCE SPECIFICATIONS LIMITS A.C. PARAMETER Input Capacitance Output Capacitance Operating Supply Current SYMBOL CIN CO ICCOP CONDITIONS f = 1Mhz All Measurements are Referenced to Device GND VCC = 5.5V, Clock Freq. = 2MHz, VIN = VCC or GND, Outputs Open NOTES 1 1 1 TEMPERATURE TA TA = +25oC = +25oC MIN MAX 25.0 25.0 2.0 UNITS pF pF mA
-55oC TA +125oC
NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Group C and D METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
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HD-6402/883 Burn-In Circuits
HD-6402/883 CERDIP
DETAIL
A
VCC
VCC
R1 C 1 2 R1 GND GND 3 R1 4 37 R1 36 R1 6 7 8 9 10 11 12 13 14 15 R1 16 17 R1 18 23 22 R1 20 21 GND 25 24 DIP HD-6402/883 35 R1 34 R1 33 R1 32 R1 31 R1 30 R1 29 R1 28 R1 27 R1 26 GND VCC GND VCC GND VCC GND GND GND VCC 40 R1 39 R1 38 R1 VCC VCC 5 VCC VCC F0
A
A A
DETAIL
B
VCC
A A
C
NOTE: ONE PER BOARD
A A A
1 2 3 4 5 6 7 4011 QUAD NAND GATE
14 13 12 11 10 9 8
A A A A
GND
B
C (NOTE 5) F0
F0 VCC
A B A
(NOTE 5)
A
19
NOTES: 1. VCC = 5.5V 0.5V 2. F0 = 100kHz 10% 3. R1 = 47k, 1/4W 10% 4. C = 0.01F minimum 5. One socket per board should not be loaded, but rather have pin 24 go the "C" of the 4011.
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HD-6402/883 Die Characteristics
DIE DIMENSIONS: 126.4 mils x 134.3 mils x 19 mils METALLIZATION: Type: Si-Al Thickness: 10kA GLASSIVATION: Type: SiO2 Thickness: 7kA
- 9kA
- 12kA
WORST CASE CURRENT DENSITY: 1.42 x 10 5 A/cm2
Metallization Mask Layout
HD-6402/883
RBR8
RRD GND NC VCC
TRC
EPE CLS1 CLS2
SBS
PI CRL TBR8
RBR7 RBR6 RBR5
TBR7
TBR6 RBR4 RBR3 RBR2 RBR1 PE TBR2 FE OE TBR TBR5 TBR4
TBR3
SFD RRC DRR DR RRI MR TBRE TBRL TRE
RO
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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